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Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
Figure 7. 16-bit NAND Interface Examples
DDR Controller
The KSZ9692PB, KSZ9692PB-S DDR memory controller provides interface for accessing external Double Data Rate
Synchronous DRAM. In addition the KSZ9692PB, KSZ9692PB-S provides two integrated DDR differential clock drivers for
a complete glueless DDR interface solution.
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Up to 200 MHz clock frequency (400 MHz data rate)
Supports one 32-bit data width bank (16-bit optional)
Up to 128MB of addressable space is available with 12 columns and 14 row address lines
Supports all DDR device densities up to 1Gb
Supports all DDR device data width x8 and x16
Configurable DDR RAS and CAS timing parameters
Two integrated JEDEC Specification JESD82-1 compliant differential clock drivers for a glueless DDR interface solution
JEDEC Specification SSTL_2 I/Os
May 2011
31
M9999-051111-4.0
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